In recent years, in information processing performances of high-end servers and routers, a bottleneck is performance of a communication circuit of an LSI for communicating with an external unit rather than performance of a CPU within the LSI. As a result, there has been increased demand for a larger capacity of electrical transmission between chips and between backboards using SerDes or the like. A high-speed signal transmission is one of means for increasing a capacity of communication. However, it is not easy to speed up signal transmission in electrical transmission through a medium such as PCB. A frequency range in which the transmission medium permits a signal to be transmitted is limited. Therefore, when a transmission signal is of a high frequency, the signal waveform greatly attenuates so that the signal cannot be detected on a receiver circuit side.
A technique for permitting high-speed signal transmission in a limited transmission band is as partial response signaling. In the partial response signaling, the frequency range of a signal can be narrowed by allowing inter-symbol interference which can be removed later through a logic operation or the like. There are various types of partial response signaling according to types of inter-symbol interference, for example, duo-binary (1+D) and modified duo-binary (1−D2). Here, D means a delay for one bit. The duo-binary (1+D) means duo-binary data obtained by adding a current data to previous duo-binary data for one bit (inter-symbol interference). In order to determine the current data in the duo-binary transmission, it is necessary to subtract the previous data for one bit from the received data. Furthermore, since inter-symbol interference occurs in the partial response signaling, the signal has more signal levels than input signal levels.
FIG. 1 is a diagram showing an eye opening in a duo-binary signal as an example of the partial response signal. It could be seen that as a result of the duo-binary signaling of a binary signal ternary eye opening is shown at a sampling timing 1401. FIG. 2 is a diagram showing a process of obtaining the originally transmitted binary data from the decision result of the duo-binary signal. The ternary output (−2, 0, 2) in the duo-binary signaling has the following data:    0: the previous bit is −1 and the current bit 1 or the previous bit is 1 and the current bit is −1,    2: the previous bit is 1 and the current bit 1,    −2: the previous bit is −1 and the current bit −1.Therefore, if the initial bit data is assumed to be “1”, the values are determined in a descending order and all data can be recovered,
FIG. 3 is a block diagram of a general partial response signaling system. The system shown in FIG. 3 is provided with a transmitter circuit 1601, a transmission medium 1602 and a receiver circuit 1603. A data input 1604 is preliminarily waveform-shaped by a transmitter side FIR filter 1606, and output to the transmission medium 1602 by an output buffer 1607. The signal passing through the transmission medium 1602 greatly attenuates and reaches the receiver circuit 1603 as a weak signal containing inter-symbol interference. This signal is converted into a digital signal at a symbol rate by a multi-bit A/D converting circuit 1608 and supplied to a receiver side FIR filter 1609. The receiver side FIR filter 1609 shapes the signal waveform to compensate inter-symbol interference caused by influence of the transmission medium. The waveform of a partial response signal 1610 outputted from the receiver side FIR filter 1609 is compared with a threshold value by a decision circuit 1611 and the decision result becomes data output 1605.
The output of the decision circuit 1611 is also supplied to an adaptive equalization control circuit 1612. The adaptive equalization control circuit 1612 outputs a control signal 1617 to adjust characteristics of the receiver side FIR filter 1609 on the basis of differential data from an expected partial response signal. The expected partial response signal is given as digital data dn within the adaptive equalization control circuit 1612 and a difference between dn and the output data yn of the receiver side FIR filter 1609 becomes differential data en. That is, the relation is expressed by an equation: en=dn−ynn adjusting method of the receiver side FIR filter 1609 in using the least mean squares method is expressed by the following equation:wn+1=wn+μ·en·yn where wn is a tap coefficient of the receiver side FIR filter 1609 and μ is an adjusting step. According to the above-mentioned equation, the coefficient wn of the receiver side FIR filter is updated. Such feedback loop formed of the receiver side FIR filter circuit 1609, the decision circuit 1611 and the adaptive equalization control circuit 1612 optimizes filter characteristics so that the output of the receiver side FIR filter 1609 may become the partial response signal.
On the other hand, the output data of the receiver side FIR filter 1609 and the output data of the decision circuit 1611 are supplied to a Mueller-Muller phase comparator 1614 in a clock data recovery circuit 1613. The Mueller-Muller phase comparator 1614 calculates whether the current clock is delayed or advanced with respect to an optimum clock and data timing by performing operation of the following equation:Δτn=yn·{circumflex over (x)}n−1+yn−1·{circumflex over (x)}n where yn is the output data of the receiver side FIR filter 1609, and{circumflex over (x)}nis the output data of the decision circuit 1611. Based on the calculation result, the phase of an oscillation circuit 1615 is adjusted and timing of a recovered clock 1616 input to the A/D converting circuit 1608 varies. Such feedback loop formed of the A/D converting circuit 1608, the receiver side FIR filter 1609, the Mueller-Muller phase comparator 1614 and the oscillation circuit 1615 controls the phase of the recovered clock 1616 to be an optimum position. By the above-mentioned mechanism, data can be accurately transmitted and received in the partial response signaling system shown in FIG. 3.
However, the system shown in FIG. 3 cannot operate at a high speed and with low power consumption due to problems of the receiver side FIR filter 1609 which is used for waveform equalization of data, and the clock data recovery circuit 1613. The reasons will be described below.
FIG. 4 is a block diagram showing an example of the FIR filter used on the receiver and transmitter sides. FIG. 4 is an example of a 6-tap FIR filter which is composed of delay circuits 1702 to 1706, multiplying circuit 1707 to 1712 and an adding circuit 1713. The delay circuits 1702 to 1706 delay data by a time period D4 corresponding to one symbol. From a data input 1701, the delay circuits 1702 to 1706 produce six data which are delayed by 0, 1D, 2D, 3D, 4D and 5D, respectively. The these data are weighted through the multiplying circuits 1707 to 1712 by WO, W1, W2, W3, W4, and W5, respectively, and supplied to the adding circuit 1713. The addition result becomes a data output 1714. As described above, in the FIR filter, addition, subtraction and multiplication need to be performed at least at a symbol rate. However, in the receiver side FIR filter, the data input 1701 becomes multi-bit digital data output from the A/D converting circuit. Since addition, subtraction and multiplication of multi-bit data require many calculations, the FIR filter cannot operate at the high speed.
On the other hand, similarly, the Mueller-Muller phase comparator used in the clock recovery circuit cannot operate at the high speed because of addition, subtraction and multiplication. However, for the clock recovery circuit, a classic binary phase comparator may be used in place of the Mueller-Muller phase comparator. By using the binary phase comparator and doubly oversampling, a high-speed clock recovery can be easily achieved. In the clock recovery using the doubly oversampling, two clocks which have 0.5 symbol timing difference from each other are used to decide a signal at data sampling points and a transition point between the data sampling points. By performing the following simple logic operation based on the decision result,upn=xor({circumflex over (x)}n−1, {circumflex over (x)}n+0.5)downn=xor(xn+0.5, {circumflex over (x)}n)a binary phase comparison result is obtained that the clock timing is down (delayed) or up (advanced) relative to the optimum timing. Here,{circumflex over (x)}n , {circumflex over (x)}n+1is a decision result at the data sampling point, and{circumflex over (x)}n+0.5is a decision result at the transition point.
However, in the partial response signaling, an accurate operation of the binary phase comparator cannot be expected. In the partial response transmission, since a frequency range of signal is narrowed by allowing removable inter-symbol interference, certain frequency components of the signal are greatly attenuated due to inter-symbol interference. Consequently, although a signal passing through the transition point is fixed to a certain value after 0.5 symbols in the normal signaling, a signal passing through the transition point is not necessarily fixed at a certain value after 0.5 symbol in the partial response signaling. That is, there is a possibility that a correct value cannot be decided.
This will be described using duo-binary signaling as an example of the partial response signal. In FIG. 5, a sample at the transition point and a sample at the signal sampling point correspond to samples at sampling timings 1801 and 1802, respectively. In the duo-binary signal in FIG. 5, since the symbol-rate signal which includes 010/101 sequence is greatly attenuated, a sufficient eye opening is not obtained at the sampling timing 1802. That is, when only the signal which varies at the symbol rate is transmitted, a correct value cannot be obtained at the sampling timing 1802. As a result, the oversampling binary phase comparator cannot perform phase comparison, and thus, clock recovery cannot be achieved.
In conjunction with the above description, a signal path monitoring method is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-95247). The signal path monitoring method in this conventional example is used when signal paths between a transmitting unit and a receiving unit which are connected by the signal paths, are monitored. A transmitting section is provided in the transmitting unit for each signal path and a receiving section is provided in the receiving unit for each signal path. In the transmitting section, a scrambler randomly codes a transmission main signal to obtain a random code sequence. A coding circuit performs partial response coding on the random code sequence to obtain a partial response code sequence. A transmission pattern detecting circuit receives partial response containing a precoder and an output code sequence from the precoder and detects whether or not a predetermined pattern exists in the output code sequence. When the predetermined pattern exists, the transmission pattern detecting circuit outputs a detection signal. When a polarity operating circuit receives the detection signal, the polarity operating circuit reverses the polarity of the partial response code sequence to obtain a reverse signal and sends the reverse signal to the signal path as a transmission signal. When the polarity operating circuit does not receive the detection signal, the polarity operating circuit sends the partial response code sequence to the signal path as the transmission signal. In the reception section, a partial response decoding circuit receives the transmission signal as a reception partial response code sequence and partial response-decodes the transmission signal to obtain a decoding signal. A descrambler descrambles the decoding signal to obtain a reception main signal. A reception pattern detecting circuit detects whether or not a predetermined pattern exists in the reception partial response code sequence and outputs a pattern detection result. A violation detecting circuit detects violation accompanied by polarity reversal according to the reception partial response code sequence and outputs a violation detection result. A monitoring section monitors abnormality of the signal path on the basis of the pattern detection result and the violation detection result.
A PRML recovery circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-262712). In this conventional example, by utilizing generation of a partial response signal by maximum likelihood sequential detection, a distance of slice level is optimally set and suitable maximum likelihood decoding is performed. A waveform equalizing circuit equalizes waveform of a read-out signal from a recording medium. A maximum likelihood decoder slices the equalized output in a +1 side slice level and a −1 side slice level to obtain a discrimination value. Then, the discrimination value is maximum likelihood decoded. A control circuit variably controls the distance between the +1 side slice level and the −1 side slice level.
Also, a high-speed serial transmission system is disclosed in Japanese Laid Open Patent Application (JP-P2002-223204A). The high-speed serial transmission system in this conventional example has a transmitting unit and a receiving unit. The transmitting unit has a pattern generating unit for generating a pseudo random pattern, a transmission circuit unit for serially converting a transmission input data and the pseudo random pattern, a transmission control unit for outputting a transmission clock control signal and a current control signal, a current control circuit for current-controlling serial data, and a transmission clock circuit for varying a transmission clock frequency. The receiving unit has a reception circuit unit for inversely transforming reception input data in parallel and outputting reception output data and the pseudo random pattern, a bit error measuring unit for measuring a bit error rate of the pseudo random pattern, a reception level detecting unit for detecting a reception level, a reception control unit for feeding back the bit error rate and characteristic data on the reception level and a reception clock circuit for generating a reception clock in synchronization with a transmission clock.
Also, a reproducing apparatus is disclosed in Japanese Laid Open Patent Application (JP-P2002-260346A). In the reproducing apparatus in this conventional example, a run length limiting code recorded in a recording medium is recovered, and a reproduction signal is subjected to partial response equalization by using a transversal filter, and decoded. For this reason, a sampling output unit distributes a signal obtained by sampling the reproduction signal or a signal obtained by further resampling and interpolating the sampling signal into an even number reproduction data signal and an odd number reproduction data signal and outputs the signals in parallel. An even number filtering unit filters the even number reproduction signal on the basis of a first tap coefficient and outputs the signal as a first waveform equalized reproduction signal. An odd number filtering unit filters the odd number reproduction signal on the basis of a second tap coefficient and outputs the signal as a second waveform equalized reproduction signal. An even number temporary determining circuit calculates a temporary determination value of an even number filtered signal and outputs a differential value between the temporary determination value and the even number filtered signal as an even number error signal. An odd number temporary determining circuit calculates a temporary determination value of an odd number filtered signal and outputs a differential value between the temporary determination value and the odd number filtered signal as an odd number error signal. A first tap coefficient generating unit variably generates the first tap coefficient of the even number filtering unit on the basis of the even number error signal and the even number reproduction signal from the even number temporary determining circuit so that the even number error signal may be minimum. A second tap coefficient generating unit variably generates the second tap coefficient of the odd number filtering unit on the basis of the odd number error signal and the odd number reproduction signal from the odd number temporary determining circuit so that the odd number error signal may be minimum. A decoding unit decodes the first waveform equalized reproduction signal outputted from the odd number filtering unit and the second waveform equalized reproduction signal outputted from the even number filtering unit.
Also, a reproducing apparatus is disclosed in Japanese Laid Open Patent Application (JP-P2003-6989A). In the reproducing apparatus in this conventional example, a signal recorded in a recording medium is reproduced and the reproduction signal is subjected to partial response equalization by using a filtering unit and decoded. In the filtering unit, a sampling unit samples the reproduction signal at a predetermined clock and outputs a sampled signal. A transversal filter delays the sampled signal to obtain multi-stage delay tap outputs, multiplies only an even number or odd number of the multi-stage delay tap outputs by the tap coefficient, adds the multiplication results and outputs it as a filtered signal. A temporary determining circuit calculates a temporary determination value of the filtered signal and outputs a differential value between the temporary determination value and the filtered signal as an error signal. A coefficient generating unit variably controls only the even number or odd number tap coefficient of the transversal filter on the basis of the error signal and the reproduction signal so that the error signal may be minimum.